Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier

ABSTRACT

A voltage multiplier comprising a chain of multiplier stages, each multiplier stage (STGj) comprising first and second inputs (IPIj, IP 2   j ) and first and second outputs (OPIj,  0 P 2   j ), which first and second outputs of a multiplier stage is coupled to respective first and second inputs of another multiplier stage, each multiplier stage (STGj) comprising a series diode arrangement of two diodes (DIj, D 2   j ) coupled, in the same current conducting direction, between the first input (IPIj) and the first output (OPIj). Each multiplier stage (STGj) further comprises a first capacitor (CIj) coupled between the first input (IPIj) and the first output (OPIj), and a second capacitor (C 2   j ) coupled between the second input (IP 2   j ) and the second output ( 0 P 2   j ). Each multiplier stage (STGj) further comprises equalizing means (VLSj; C 2   j , C 3   j , C 4   j ), preferably capacitors (Csj), for equalizing the current distributions, as a function of time, of the currents (Ij) through the diodes (DIj, D 2   j ).

The present invention relates in general to voltage multipliers forconverting a relatively low AC-voltage into a relatively highDC-voltage. Such a voltage multiplier can be used in all kinds ofequipments having a component or module which must be powered by a highDC-voltage. Such a component can for instance be a cathode ray tube in atelevision or a computer. Voltage multipliers are also used in laser andplasma generator applications.

More particularly, the present invention relates to X-ray apparatuswhich comprise an X-ray tube for generating X-rays, said X-ray tubeneeding a device for powering the X-ray tube with a high DC-voltage.

Voltage multipliers for converting a low AC-voltage into a highDC-voltage are widely used. The so-called “Cockroft and Walton” cascaderectifiers are used for several decades. Such a voltage multiplier isconstructed by a series of rectifier diodes and capacitors to form avoltage multiplier i.e. a circuit that transforms an AC input voltageinto an N-times higher DC-voltage, N being the number of rectifierstages. Such a voltage multiplier is for instance disclosed in FIG. 5 ofthe Japanese patent application JP3028270A wherein the first stage iscomposed of diodes D1 and D2, and capacitors C1 and C5; the second stageis composed of diodes D3 and D4, and capacitors C2 and C6, etcetera.Each stage increases the DC-voltage supplied by its previous stageexcept of the first stage which receives the AC-input voltage andgenerates a DC-voltage.

There is generally a need for developing voltage multipliers having ahigh power efficiency to avoid unnecessary power consumption and heatproduction. This is especially the case for portable applications. Amain reason for poor power efficiency is the energy loss in the diodes,especially when a high operation frequency is used. In X-ray apparatusthe DC-voltage needed for the X-ray tube is usually very high, e.g. 75kV. In CT (Computer Tomography) applications a high power X-ray beam isneeded for e.g. up to 20 seconds. This requires a so-called rotatinganode tube, having its anode on ground potential and the cathode on e.g.−150 kV. Such a high voltage cannot reasonably be handled by theinsulation of a transformer. Therefore voltage multipliers are appliedleaving the transformer at a lower voltage, for instance 40 kV.

Ageing tubes suffer increasingly from tube arching which is a disruptivedischarge caused by growing spurious gases and impurities in the tube.Usually an arching current is limited by resistors and detected bycontrol electronics which can switch off the high voltage generator,e.g. the voltage multiplier. However the voltage multiplier has someoutput capacitance. In many cases this output capacitance is evenincreased on purpose by the addition of a smoothing capacitor tominimize the AC-ripple voltage in the DC-output voltage. Therefore, evenif the voltage multiplier is switched off by the control electronics,the charge of the output capacitance causes a discharge current throughthe tube. This could still damage the tube. Therefore there is a need toreduce the output capacitance of the voltage multiplier. However thisoutput capacitance can only be lowered if the operating frequency (thusthe AC-input voltage of the multiplier) is increased. Otherwise theAC-ripple voltage would become too high. However, without additionalmeasures, the power efficiency of the voltage multiplier would bereduced because of the increased operation frequency which causesincreased energy losses in the diodes.

It is therefore an object of the invention to provide a voltagemultiplier with increased power efficiency.

In an embodiment of the invention the voltage multiplier comprises achain of multiplier stages, each multiplier stage comprising first andsecond inputs and first and second outputs, which first and secondoutputs of a multiplier stage is coupled to respective first and secondinputs of another multiplier stage except for a last multiplier stage,which first and second inputs of a first multiplier stage constitutefirst and second inputs of the chain, each multiplier stage comprising aseries diode arrangement of two diodes coupled, in the same currentconducting direction, between the first input and the first output, andequalizing means for equalizing the current distributions, as a functionof time, of the currents through the diodes.

The invention is based on the insight that in the conventional voltagemultiplier the currents through the conducting diodes occur,approximately, one after each other. This leads to a waveform of sharppulses which causes a considerable energy loss in the diodes. In theinventive voltage multiplier these pulses occur more or lesssimultaneously and are also less steep because they are spread out overtime. As a consequence energy losses in the diodes are reduced whichresult in an increased power efficiency of the voltage multiplier.

In a further embodiment of the invention the voltage multiplier ischaracterized in that each multiplier stage comprises a first capacitorcoupled between the first input and the first output, and a secondcapacitor coupled between the second input and the second output, andthat in at least one of the multiplier stages the equalizing meanscomprises a time dependent voltage level-shifter coupled between thesecond output and a conjunction point of the two diodes, and in theremaining multiplier stages the equalizing means comprises an electricalcoupling between the second output and a conjunction point of the twodiodes.

The time dependent voltage level-shifters are preferably designed in away that the average voltage is about zero, and thus the level-shiftersare only functioning as a voltage drop for the AC-component of thediodes. For this reason the time dependent voltage level-shifters arepreferably implemented by voltage level-shift capacitors. By doing so itis possible, if appropriately dimensioned, to cause equal currentdistributions, or even equal currents, through the conducting diodes inall the multiplier stages.

Although level-shift capacitors functioning as the time dependentvoltage level-shifters are highly preferred other means can alsofunction as a time dependent voltage level-shifter, e.g. a resistorbiased by a time dependent current. It is to be noted that Japanesepatent application JP63240374A discloses in FIG. 1 a voltage multiplierwhich is provided with resistors in the current paths to the diodes.These resistors are however not biased by a time-dependent current andthus do not function in the way as in the inventive voltage multiplier.Thus these resistors do not fall under the definition of a timedependent voltage level-shifter as used in the current invention. InJP63240374A the resistors only serve to reduce the rush currents throughthe diodes. Although this also helps a little bit to increase the powerefficiency, the waveforms through the diodes are still steep and followeach other successively thereby causing a substantial amount of energyloss, in contrast to the inventive voltage multiplier.

In another further embodiment of the invention a group of threeconnected capacitors in a so-called “star arrangement” are replaced bythree capacitors in a so-called “triangle arrangement”. The function ofthe voltage multiplier is not changed if the three capacitors aredimensioned properly. How the dimensioning of the three capacitors inthe “triangle arrangement” must be derived from the “star arrangement”is obvious since the so-called “star-triangle transformation” is a wellknown technique which is for instance described in the Dutch textbook:“ELEKTRISCHE NETWERKEN” by the author: ir. A. Henderson, published by“Delftse Uitgevers Maatschappij”, 3th edition 1981, chapter 2, paragraph7, pages 54-57.

In all embodiments of the invention a smoothing capacitor may optionallybe added which is coupled between the first output of the lastmultiplier stage and the first input of the first multiplier stage.

The invention can be applied in both half wave and full wave voltagemultipliers. If a full wave multiplier is used the capacitors coupledbetween the first output and the first input of a multiplier stage canbe left out, especially when at the same time there is chosen for theoption to add the smoothing capacitor.

The invention will be described in more detail with reference to theaccompanying drawings, in which:

FIG. 1 shows a conventional half wave voltage multiplier;

FIG. 2 shows a conventional full wave voltage multiplier;

FIG. 3 shows a diagram of the electrical currents through the diodes ofthe conventional half wave voltage multiplier according to FIG. 1 orthrough the diodes of the upper or under half of the full wave voltagemultiplier of FIG. 2;

FIG. 4 shows a diagram of the electrical currents through the diodes ofa half wave voltage multiplier according to the invention or through thediodes of the upper or under half of a full wave voltage multiplieraccording to the invention;

FIG. 5 shows an electrical schematic of a first inventive embodiment ofa half wave or full wave voltage multiplier (corresponding to claim 2)provided with voltage level-shift capacitors in the current paths to thediodes;

FIG. 6 shows an electrical schematic of a second inventive embodiment ofa half wave or full wave voltage multiplier (corresponding to claim 3)having a reduced number of capacitors compared to the first embodiment;

FIG. 7 shows an electrical schematic of a third inventive embodiment ofa half wave or full wave voltage multiplier (corresponding to claim 4)which differs from the first embodiment in that so-called “star-triangletransformations” for groups of three connected capacitors are applied;

FIG. 8 shows an electrical schematic of a fourth inventive embodiment ofa half wave or full wave voltage multiplier (corresponding to claim 5)having a reduced number of capacitors compared to the third embodiment;

FIG. 9 shows an electrical schematic of a fifth inventive embodiment ofa full wave voltage multiplier (corresponding to claim 6);

FIG. 10 shows an electrical schematic of a sixth inventive embodiment ofa full wave voltage multiplier (corresponding to claim 7) having areduced number of capacitors compared to the fifth embodiment;

FIG. 11 shows an electrical schematic of a seventh inventive embodimentof a full wave voltage multiplier (corresponding to claim 8) whichdiffers from the fifth embodiment in that so-called “star-triangletransformations” for groups of three connected capacitors are applied;

FIG. 12 shows an electrical schematic of an eight inventive embodimentof a full wave voltage multiplier (corresponding to claim 9) having areduced number of capacitors compared to the seventh embodiment;

FIG. 13 shows a schematic of a ninth inventive embodiment of a half waveor full wave voltage multiplier, having N stages, provided with asmoothing capacitor coupled between an output of the last multiplierstage and an input of the first multiplier stage;

FIG. 14 shows a schematic of an X-ray apparatus comprising a device forgenerating a high voltage which comprises the inventive voltagemultiplier for supplying a high voltage between an anode and a cathodeof an X-ray tube; and

FIG. 15 shows a schematic of an apparatus comprising a cathode ray tubefor generating an image on a screen which comprises a device forgenerating a high voltage which comprises the inventive voltagemultiplier for supplying one or more high voltages between electrodes ofthe cathode ray tube.

In these figures parts or elements having like functions or purposesbear the same reference symbols. So for instance the first capacitor C₂₁of stage STG₁ in FIG. 9 has the same function as the second capacitorC₂₁ of stage STG₁ in FIG. 5.

FIG. 1 shows a conventional half wave voltage multiplier VM whichcomprises in general a chain of N multiplier stages STG₁-STG_(N).

Throughout the application an integer j is used to refer to a specificstage (stage STG_(j)). Thus for instance capacitor C_(1j) is in generalan indication of capacitor C₁ in the j^(th) stage STG_(j), and morespecifically C₁₁ (j=1) means capacitor C₁ in the 1^(th) stage STG₁, C₁₂(j=2) means capacitor C₁ in 2^(th) stage STG₂, C_(1N) (j=N) meanscapacitor C_(N) in N^(th) (=last) stage STG_(N), and so on. Henceforththe integer N will be 4 throughout the description to the Figures by wayof example. The integer N can however be chosen freely. The appropriatevalue for N should be chosen in accordance with the amplitude of an ACinput voltage U₁ between first and second inputs IVM₁, IVM₂ of the chainand the desired value of a DC-output voltage on a node of the chain.This node can for instance be the output OP of the chain.

Each stage STG_(j) comprises first and second inputs IP_(1j), IP_(2j)and first and second outputs OP_(1j), OP_(2j). The first and secondinputs IP₁₁, IP₂₁ of the first stage STG₁ constitute the inputs IVM₁,IVM₂. The first and second outputs OP_(1j), OP_(2j) of a stage STG_(j)is connected to respective first and second inputs IP_(1j), IP_(2j) ofanother stage STG_(j) except for the last stage STG₄. Each multiplierstage STG_(j) comprises a first capacitor C_(1j) which is connectedbetween the first input IP_(1j) and the first output OP_(1j), and asecond capacitor C_(2j) which is connected between the second inputIP_(2j) and the second output OP_(2j). Each multiplier stage STG_(j)further comprises a series diode arrangement of two diodes D_(1j),D_(2j) which is connected between the first input IP_(1j) and the firstoutput OP_(1j). For instance in the first stage STG₁ a first diode D₁₁is connected with its anode to the first input IP₁₁ and with its cathodeto the anode of a second diode D₂₁. The cathode of the second diode D₂₁is connected with the output OP₁₁. The anodes and cathodes of D₁₁ andD₂₁ may also all be reversed. The diodes D₁₁ and D₂₁ should have thesame current conducting direction. Thus the conjunction point of thediode series arrangement of D₁₁ and D₂₁ is always formed by an anode anda cathode of D₁₁ and D₂₁. The same applies for all the other stagesSTG_(j). Moreover the current conducting directions of all the diodes inthe voltage multiplier VM should be equal. It basically means that allthe diodes in the voltage multiplier VM are connected in series in thesame current conducting direction. The current through the first diodeD_(1j) in each stage STG_(j) is indicated by I_(j). In each stageSTG_(j) the conjunction point of the series diode arrangement isconnected with the first output OP_(2j).

The principle of operation of this half wave voltage multiplier VM isgenerally known from the prior art. Briefly summarized the operation isas follows. Assume that a periodic AC-input voltage U₁ is availablebetween the first and second inputs IVM₁, IVM₂. This input voltage isusually sinusoidal. However also other waveforms can be used. If, in theexample of FIG. 1, the potential (voltage) at the second input IVM₂ ishigher than the potential at the first input IVM₁, diode D₁₁ willconduct current and as a consequence the capacitor C₂₁ will be charged.When the top value of the potential at the second input IVM₂ is reached,C₂₁ will be fully charged. Then the voltage on IVM₂ will start lowering.As a consequence D₁₁ will become non-conducting because the voltageacross C₂₁ will, initially, remain constant. Moreover at the same timethat the potential at IVM₂ lowers, the potential at IVM₁ increases. Soafter half a time period of the periodic AC-input voltage U₁, thepotentials at the inputs IVM₁ and IVM₂ are reversed, i.e. the potentialat IVM₁ has reached the top value, and the potential at IVM₂ has reachedthe minimum value (negative top value). During the last half-period ofthe potential reversing process diode D₂₁ was conducting andtransferring part of the charge of C₂₁ to C₁₁. After numerous periods ofthe periodic AC-input voltage U₁, the voltage multiplier VM has reachedthe so called “steady state” and all the first capacitors C_(1j) and allthe second capacitors C_(2j) will be fully charged. The voltages acrosseach first capacitor will be approximately equal to twice thepeak-to-peak value of the AC-input voltage U₁. Therefore since in FIG. 1four stages (N=4) are used, the DC-output voltage between the output OPand the second input IVM₂ of the voltage multiplier VM will beapproximately equal to eight times the peak-to-peak value of theAC-input voltage U₁.

In the above explanation it was assumed that the voltage multiplier VMwas not coupled to an output load. If for instance an X-ray tube iscoupled to e.g. the output OP then the voltages on the capacitors willdecrease and consequently the output voltage at the output OP willdecrease. The output voltage will then also be burdened with a ripple.The output voltage decreases and at the same time the ripple voltageincreases with increasing output (load) current. However the higher thevalues of both the first and second capacitor C_(1j), C_(2j) in eachstage STG_(j) the less the output voltage decreases and the less theripple voltage increases. However for i.a. weight reasons of the voltagemultiplier the capacitance values should not be chosen higher thannecessary.

FIG. 2 shows a conventional full wave voltage multiplier VM. Itbasically comprises two half-wave voltage multipliers which are mergedtogether thereby sharing the first capacitor C_(1j) in each stageSTG_(j). The stages STG_(j) (which correspond to FIG. 1) are indicatedwith dashed rectangles. In addition to the embodiment of FIG. 1 eachstage STG_(j) comprises a further series diode arrangement of two diodesD_(1jA), D_(2jA), and a third capacitor C_(2jA). An element having areference sign which finishes with the character “A” corresponds to andhas similar function as a corresponding element having a like referencesign but without the finishing character “A”. Thus for instance diodeD_(11A) has similar function as the diode D₁₁.

This full wave voltage multiplier VM comprises a third input IVM₃. InFIG. 2 a transformer T is shown having a primary winding and a secondarywinding. This transformer T is used to transform an AC-voltage, betweenthe terminals of the primary winding (not shown in FIG. 2), to an ACinput voltage U_(i), between the second input IVM₂ and the third inputIVM₃ of the voltage multiplier VM. The AC input voltage U_(i) ispreferably chosen as high as possible but not so high that theinsulation of the transformer T can not handle it. The voltagemultiplier VM further transforms this AC input voltage U_(i) to an evenhigher, and also rectified, output voltage at for instance the outputterminal OP.

An advantage of the full wave voltage multiplier compared to the halfwave voltage multiplier is that the ripple in the output voltage isreduced. Optionally the secondary winding of the transformer T may beprovided with a midpoint which is connected (indicated by dashed lines)to the first input IVM₁. If this midpoint is used as reference voltagee.g. by grounding it, the maximum absolute voltage on any point in thesecondary winding is never higher than half the peak-to peak voltage ofthe AC input voltage U_(i). This is advantage with respect to theinsulation of the transformer T. The voltage difference between thesecond input IVM₂ and the first input IVM₁ is indicated by U₁ and thevoltage difference between the first input IVM₁ and the third input IVM₃is indicated by U₂.

FIG. 3 shows a diagram of the electrical currents through the diodes ofthe conventional half wave voltage multiplier VM according to FIG. 1 orthrough the diodes of the upper or under half of the full wave voltagemultiplier VM of FIG. 2. So by way of example and referring to FIG. 1,the currents I_(I), I₂, I₃, and I₄ through respectively diodes D₁₁, D₁₂,D₁₃, and D₁₄ are indicated in FIG. 3 in the situation that the voltagemultiplier VM has reached its steady state. As is clear form FIG. 3 thecurrents I₁, I₂, I₃, and I₄ more or less succeed each other and togetherform a waveform of sharp pulses which causes a considerable energy lossin the diodes D₁₁, D₁₂, D₁₃, and D₁₄. This waveform of sharp pulsesoccurs during one half of the AC input voltage U_(i) in which thevoltage on the second input IVM₂ is higher than the voltage on the firstinput IVM₁. During the other half of the AC input voltage U_(i) in whichthe voltage on the first input IVM₁ is higher than the voltage on thesecond input IVM₂, a similar waveform of sharp pulses occurs caused bymore or less succeeding currents (not indicated in the Figures) throughrespectively the diodes D₂₁, D₂₂, D₂₃, and D₂₄.

FIG. 5 shows an electrical schematic of a first inventive embodiment ofa half wave or full wave voltage multiplier VM. The difference with theschematic of FIG. 2 is that the voltage multiplier VM in additioncomprises equalizing means for equalizing the current distributions, asa function of time, of the currents I_(j) through the diodes D_(1j),D_(2j) and in case of the full wave version the equalizing means mayalso equalize the current distributions, as a function of time, of thecurrents I_(jA) through the diodes D_(1jA), D_(2jA). In the following,by way of example, the functioning of this circuit is explained byreferring only to the half-wave voltage multiplier VM indicated insidethe dashed rectangles. The equalizing means comprises, preferably ineach stage STG_(j), a time dependent voltage level-shifter VLS_(j)coupled between the second output OP_(2j) and a conjunction point of thetwo diodes D_(1j), D_(2j). Preferably, and most easily, the timedependent voltage level-shifter VLS_(j) is implemented by a voltagelevel-shift capacitor C_(sj). Although recommended, it is not strictlynecessary to put in a voltage level-shift capacitor C_(sj) in everystage in order to get an enhanced power efficiency with respect to theconventional voltage multipliers.

FIG. 6 shows an electrical schematic of a second inventive embodiment ofa half wave or full wave voltage multiplier having a reduced number ofcapacitors compared to the first embodiment. The difference with thefirst embodiment as shown in FIG. 5 is that in the first stage STG₁ thesecond capacitor C₂₁ is replaced by an electrical connection and in thelast stage STG₄ the voltage level-shift capacitor C_(s4) is alsoreplaced by an electrical connection. For the last stage STG₄ it meansthat the second capacitor C₂₄ takes over the function of the level-shiftcapacitor C_(s4) (in FIG. 5). The operation of the circuits of FIGS. 5and 6 are similar.

By way of example the dimensioning of the voltage level-shift capacitorsC_(sj) is explained with reference to FIG. 6. It is assumed that all thediodes have approximately the same I-V characteristics since this leadsto the best results. In the explanation it is assumed that currents areflowing through the diodes D₁₁, D₁₂, D₁₃, and D₁₄ during one half-periodof the AC input voltage U_(i). (During the other half-period of the ACinput voltage U_(i) the diodes D₂₁, D₂₂, D₂₃, and D₂₄ are conductingcurrent in stead of the diodes D₁₁, D₁₂, D₁₃, and D₁₄, calculationsduring this half-period of the AC input voltage U_(i) will lead to thesame results.) For getting the best enhancement in power efficiency itis the desire to transform the sharp waveform of pulses as indicated inFIG. 3 into a less sharp wave form of pulses wherein the currents I_(j)occur approximately in the same time instant, see FIG. 4. With regard tothe currents I_(j) equation [1] is valid:

∀j: I_(j)=I  [1]

As a consequence the currents through capacitors C₂₄, C_(s3), C_(s2),and C_(s1) equal I, the current through capacitor C₂₃ equals 2I, and thecurrent through capacitor C₂₂ equals 3I. Further as a consequence ofequation [1] the voltage drops across the diodes D₁₁, D₁₂, D₁₃, and D₁₄are equal. With above mentioned information complemented with thegeneral known physical laws (especially with Kirchoff's 1st and 2stLaws) any person skilled in electronics can calculate the requiredrelation between the capacitors C_(sj) and the capacitors C_(2j).

Especially for X-ray applications a high dynamic response of the voltagemultiplier is preferred. This dynamic response can be optimized bybalancing the ripple voltages across the capacitors C_(2j). This can bedone by choosing a same capacitor value C for each capacitor C_(2j) asexpressed in equation [2]:

∀j: C_(2j)=C  [2]

Under the assumption of equation [2] a general equation for thecapacitor C_(sj) can be derived and is shown in equation [3]:

$\begin{matrix}{{\forall{{j\; 1} \leq j \leq {N - {1\text{:}\mspace{14mu} C_{sj}}}}} = \frac{C}{\sum\limits_{k = j}^{N - 1}( {N - k} )}} & \lbrack 3\rbrack\end{matrix}$

If for instance N=4 (four stages are used as in the Figures) thefollowing equation [4] results from equation [3]:

$\begin{matrix}{{\forall{{j\; 1} \leq j \leq {3\text{:}\mspace{14mu} C_{sj}}}} = \frac{C}{\sum\limits_{k = j}^{C}( {4 - k} )}} & \lbrack 4\rbrack\end{matrix}$

which results in the following values for capacitors C_(sj):

j = 3 ⇒ C_(s 3) = C$j = { 2\Rightarrow C_{s\; 2}  = \frac{C}{3}}$$j = { 1\Rightarrow C_{s\; 1}  = \frac{C}{6}}$

FIG. 7 shows an electrical schematic of a third inventive embodiment ofa half wave or full wave voltage multiplier VM. It differs (for the halfwave multiplier) with the first embodiment as shown in FIG. 5 in that ineach stage STG_(j) the capacitors C_(sj) are replaced by a seriescapacitor arrangement of a third and a fourth capacitor C_(3j), C_(4j)connected between the second input IP_(2j) and the second output OP_(2j)and that a conjunction point of the series capacitor arrangement isconnected to the conjunction point of the series diode arrangement.

As previously stated it is generally known (see e.g. “ELEKTRISCHENETWERKEN”) how a group of three connected capacitors in a so-called“star arrangement” can be replaced by three capacitors in a so-called“triangle arrangement”. From FIG. 5 it is clear that e.g. capacitorsC₂₁, C_(s1), and C₂₂ form a “star arrangement” which can be transformedinto a “triangle arrangement” formed by the capacitors C₂₁, C₃₁, and C₄₁in FIG. 7. However capacitors C₂₁, C_(s1), and C₂₂ (FIG. 5) are not allin the same stage. This makes it difficult to make the transformationsfor all the capacitors C_(2j) and C_(sj), since then for instance thesecond stage would only be left with the capacitor C_(s2). Thereforegenerally the preferred way to perform the translations is to split(just in mind) each capacitor C_(2j) into a series arrangement of twocapacitors wherein the respective series arrangement has the samesubstitution value of the total capacitance as the capacitance of the“original” single capacitor C_(2j). Although not necessary it ispreferred and most convenient to use (just in mind) two capacitors inseries each having twice the capacitance value of the “original” singlecapacitor C_(2j). Then it can be easily seen that each stage STG_(j) inFIG. 5 can be thought of comprising a “star arrangement” which caneasily be transformed into a “triangle arrangement” (see FIG. 7).Special attention is needed for the first stage STG₁ in which it is notappropriate to split (just in mind) capacitor C₂₁ into two parts,because capacitor C₂₁ is not connected to another stage but to thesecond input IVM₂. Also special attention is needed for the last stageSTG₄ which has of course no connection to a higher order stage. Thus the“missing” capacitor should (just in mind) be added and to be connectedwith one end to the conjunction point of capacitor C₂₄ and capacitorC_(s4), and the other end leaving unconnected.

FIG. 8 shows an electrical schematic of a fourth inventive embodiment ofa half wave or full wave voltage multiplier having a reduced number ofcapacitors compared to the third embodiment as shown in FIG. 7. Thedifference with the third embodiment as shown in FIG. 7 is that in thefirst stage STG₁ the capacitors C₂₁ and C₃₁ are left out, and anelectrical connection is made between the second input IP₂₁ and thesecond output OP₂₁, and in the last stage STG₄ the capacitors C₂₄, C₃₄,and C₄₄ are left out, and an electrical connection is made between thesecond input IP₂₄, the second output OP₂₄, and the conjunction point ofthe series diode arrangement. A skilled person in electronics is ableand may, if necessary, adapt the values of the capacitors, in order toagain acquire the optimum enhancement in power efficiency under the sameprinciples as explained previously with reference to the equations [1]and [2].

FIG. 9 shows an electrical schematic of a fifth inventive embodiment ofa full wave voltage multiplier VM. A difference with the firstembodiment as shown in FIG. 5 is that in this fifth embodiment the firstcapacitors C_(1j) of FIG. 5 are left out in FIG. 9. This is however onlypossible in a full wave voltage multiplier. (Compare the dashedrectangles of FIG. 9 with the dashed rectangles of FIG. 5.) Therefore inFIG. 9 each multiplier stage STG_(j) also comprises the diodes D_(1jA)and D_(2jA) of the further series diode arrangement and a furtherlevel-shift capacitors C_(s1A). The advantage of the fifth embodimentover the second embodiment is the reduction in size and weight of a fullwave voltage multiplier VM. For the purpose of claim 6 in each stageSTG_(j) now capacitor C_(2j) is referred to as the first capacitor, andcapacitor C_(2jA) is referred to as the second capacitor.

FIG. 10 shows an electrical schematic of a sixth inventive embodiment ofa full wave voltage multiplier having a reduced number of capacitorscompared to the fifth embodiment. The difference with the fifthembodiment as shown in FIG. 9 is that in the first stage STG₁ the firstcapacitor C₂₁ is replaced by an electrical connection, the secondcapacitor C_(21A) is replaced by an electrical connection, and in thelast stage STG₄ the voltage level-shift capacitor C_(s4) is replaced byan electrical connection, and the further level-shift capacitor C_(s4A)is replaced by an electrical connection. For the last stage STG₄ itmeans that the first capacitor C₂₄ takes over the function of thelevel-shift capacitor C_(s4) (in FIG. 9), and the second capacitorC_(24A) takes over the function of the further level-shift capacitorC_(s4A) (in FIG. 9). The operation of the circuits of FIGS. 9 and 10 aresimilar.

FIG. 11 shows an electrical schematic of a seventh inventive embodimentof a full wave voltage multiplier. The difference with the thirdembodiment as shown in FIG. 7 is that in this seventh embodiment thefirst capacitors C_(1j) of FIG. 7 are left out in FIG. 11. This ishowever only possible in a full wave voltage multiplier. Therefore inFIG. 11 each multiplier stage STG_(j) must also comprise diodes D_(1jA)and D_(2jA) of the further series diode arrangement and the capacitorsC_(3jA) and C_(4jA) of the further series capacitor arrangement.(Compare the dashed rectangles of FIG. 11 with the dashed rectangles ofFIG. 7.) The advantage of the seventh embodiment over the thirdembodiment is the reduction in size and weight of a full wave voltagemultiplier VM. For the purpose of claim 8 in each stage STG_(j) nowcapacitor C_(2j) is referred to as the first capacitor, capacitorC_(2jA) is referred to as the second capacitor, capacitor C_(3j) isreferred to as the third capacitor, capacitor C_(4j) is referred to asthe fourth capacitor, capacitor C_(3jA) is referred to as the fifthcapacitor, and capacitor C_(4jA) is referred to as the sixth capacitor.

FIG. 12 shows an electrical schematic of an eight inventive embodimentof a full wave voltage multiplier. The difference with the seventhembodiment as shown in FIG. 11 is that in the first stage STG₁ thecapacitors C₂₁, C₃₁, C_(21A), and C_(31A) are left out, an electricalconnection is made between the second input IP₂₁ and the second outputOP₂₁, and an electrical connection is made between the third input IP₃₁and the third output OP₃₁, and in the last stage STG₄ the capacitorsC₂₄, C₃₄, C₄₄, C_(24A), C_(34A), and C_(44A) are left out, an electricalconnection is made between the second input IP₂₄, the second outputOP₂₄, and the conjunction point of the series diode arrangement, and anelectrical connection is made between the third input IP₃₄, the thirdoutput OP₃₄, and the conjunction point of the further series diodearrangement. A skilled person in electronics is able and may, ifnecessary, adapt the capacitors, in order to again acquire the optimumenhancement in power efficiency under the same principles as explainedpreviously with reference to the equations [1] and [2].

FIG. 13 shows a schematic of a ninth inventive embodiment of a half waveor full wave voltage multiplier VM, having N stages, provided with asmoothing capacitor C₀ which is connected between an output OP_(1N) ofthe last multiplier stage STG_(N) and the input IP₁₁ of the firstmultiplier stage STG₁. In some applications it is advantageous to applythis smoothing capacitor C₀ to further reduce the ripple in the outputvoltage. It may especially be advantageous in the fifth, sixth, seventh,and eight embodiments as shown in respectively FIGS. 9, 10, 11, and 12since in these embodiments the capacitors C_(1j) are left out. It is tobe noted however that usually a parasitic capacitance which serves asthe (or part of the) smoothing capacitor C₀ is present by a (partially)capacitive load which is connected to e.g. the output OP. Such acapacitive load can for instance be a high voltage connection cablebetween the output OP and an X-ray tube (and the X-ray tube itself).

FIG. 14 shows an example of a schematic of an X-ray apparatus XRcomprising a device for generating a high voltage which comprises theinventive voltage multiplier VM for supplying a high voltage between ananode A and a cathode C of a glass vacuum X-ray tube XRT. The voltagemultiplier VM supplies from the output OP, via a cable CBL, a positivehigh voltage to the anode A. The cathode C is grounded and is thus, inthis example, connected to the midpoint of the transformer T. (It isalso possible to ground the anode A and to supply a high negativevoltage to the cathode C.) The cathode C is a heated filament. Duringoperation current passes through the filament, heating it up. The heatsputters electrons off of the filament surface. The positively chargedanode A, which is usually a flat disc made of tungsten, draws theelectrons across the tube XRT. The voltage difference between the anodeA and the cathode C is extremely high, so the electrons (electron beamEB) fly through the tube XRT with a great deal of force. When a speedingelectron collides with a tungsten atom, it knocks loose an electron inone of the atom's lower orbitals. An electron in a higher orbitalimmediately falls to the lower energy level, releasing its extra energyin the form of a photon. Since it is a big drop the photon has a highenergy level, thus it is an X-ray photon. The high-impact collisionsinvolved in the X-ray production generate a lot of heat. For this reasona motor M rotates the anode A so that the electron beam EB is not alwaysfocused on the same area of the anode A. By this it is avoided that(part of) the anode A will melt. A cool oil bath OB surrounding theenvelope also absorbs heat. The tube XRT is surrounded by a thick leadshield PB. This keeps the X-rays from escaping in all directions. Asmall window in the shield PB lets some of the X-ray photons escape in anarrow X-ray beam XRB. The beam XRB passes through a series of filters Fon its way to e.g. a patient.

FIG. 15 shows a schematic of an apparatus comprising a cathode ray tubeCRT for generating an image on a screen SCR which comprises a device forgenerating a high voltage which comprises the inventive voltagemultiplier VM for supplying one or more high voltages between electrodesof the cathode ray tube. CRT's are for instance used in TV's, computermonitors, oscilloscopes, spectrum analyzers etcetera. In this examplethe CRT comprises a cathode C which can emit an electron beam EB towardsthe screen SCR due by high positive voltages (with respect to thecathode C) on the anodes A₁, A₂, A₃, A₄, and A₅. Focusing coils FCLSfocus the beam EB, and deflection coils DCLS deflect the beam EB, sothat a sharp and well-formed image is transmitted from the screen SCR.In this example the CRT needs several high voltages, of which some havedifferent values, on the anodes A₁, A₂, A₃, A₄, and A₅. For this reasonthe voltage multiplier VM is provided with a multiple of outputs: outputOP (with the highest high voltage) connected to the anodes A₁, outputsOP_(A) and OP_(B) (with the lowest high voltages) connected to theanodes A₄ and A₅, and outputs OP_(C) and OP_(D) (with intermediate highvoltages) connected to the anodes A₂ and A₃.

It is possible to apply the so-called “star-triangle transformations”for groups of connected capacitors for only part of the multiplierstages STG_(j), thus mixed configurations are possible e.g. a mix ofstages from the first (FIG. 5) and third (FIG. 7) embodiments can beused to construct a voltage multiplier.

It is to be noted that in order to reduce the generation of EMI (ElectroMagnetic Interference) an EMI-series arrangement of a resistor and acapacitor may be connected in series with at least one of the first,second and third inputs IVM₁, IVM₂, IVM₃ of the voltage multiplier VM.In case of the full wave embodiments in which the transformer T isprovided with a midpoint the EMI-series arrangement is preferablyconnected in between the first input IVM₁ of the voltage multiplier VMand the midpoint of the transformer T.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and those skilled in the art will becapable of designing alternative embodiments without departing from thescope of the invention as defined by the appended claims. In the claims,any reference signs placed in parentheses shall not be construed aslimiting the claims. The words “comprising” and “comprises”, and thelike, do not exclude the presence of elements other than those listed inany claim or in the application as a whole. The singular reference of anelement does not exclude the plural reference of such elements. The merefact that certain measures are recited in mutually different dependentclaims does not indicate that a combination of these measures can not beused.

1. A voltage multiplier comprising a chain of multiplier stages(STG₁-STG_(N)), each multiplier stage (STG_(j)) comprising first andsecond inputs (IP_(1j), IP_(2j)) and first and second outputs (OP_(1j),OP_(2j)), which first and second outputs (OP_(1j), OP_(2j)) of amultiplier stage (STG_(j)) is coupled to respective first and secondinputs (IP_(1j), IP_(2j)) of another multiplier stage (STG_(j)) exceptfor a last multiplier stage (STG_(N)), which first and second inputs(IP₁₁, IP₂₁) of a first multiplier stage (STG₁) constitute first andsecond inputs (IVM₁, IVM₂) of the chain, each multiplier stage (STG_(j))comprising a series diode arrangement of two diodes (D_(1j), D_(2j))coupled, in the same current conducting direction, between the firstinput (IP_(1j)) and the first output (OP_(1j)), and equalizing means(VLS_(j); C_(2j), C_(3j), C_(4j)) for equalizing the currentdistributions, as a function of time, of the currents (I_(j)) throughthe diodes (D_(1j), D_(2j)).
 2. A voltage multiplier according to claim1, characterized in that each multiplier stage (STG_(j)) comprises afirst capacitor (C_(1j)) coupled between the first input (IP_(1j)) andthe first output (OP_(1j)), and a second capacitor (C_(2j)) coupledbetween the second input (IP_(2j)) and the second output (OP_(2j)), andthat in at least one of the multiplier stages (STG_(j)) the equalizingmeans comprises a time dependent voltage level-shifter (VLS_(j)) coupledbetween the second output (OP_(2j)) and a conjunction point of the twodiodes (D_(1j), D_(2j)), and in the remaining multiplier stages theequalizing means comprises an electrical coupling between the secondoutput (OP_(2j)) and a conjunction point of the two diodes (D_(1j),D_(2j)).
 3. A voltage multiplier according to claim 1, characterized inthat each multiplier stage (STG_(j)) comprises a first capacitor(C_(1j)) coupled between the first input (IP_(1j)) and the first output(OP_(1j)), each multiplier stage (STG_(j)) except for a first multiplierstage (STG₁) comprises a second capacitor (C_(2j)) coupled between thesecond input (IP_(2j)) and the second output (OP_(2j)), and in that thefirst multiplier stage (STG₁) comprises an electrical coupling betweenthe second input (IP₂₁) and the second output (OP₂₁), and that, in atleast one of the multiplier stages (STG_(j)) the equalizing meanscomprises a time dependent voltage level-shifter (VLS_(j)) coupledbetween the second output (OP_(2j)) and a conjunction point of the twodiodes (D_(1j), D_(2j)), and in the remaining multiplier stages theequalizing means comprises an electrical coupling between the secondoutput (OP_(2j)) and a conjunction point of the two diodes (D_(1j),D_(2j)).
 4. A voltage multiplier according to claim 1, characterized inthat each multiplier stage (STG_(j)) comprises a first capacitor(C_(1j)) coupled between the first input (IP_(1j)) and the first output(OP_(1j)), a second capacitor (C_(2j)) coupled between the second input(IP_(2j)) and the second output (OP_(2j)), a series capacitorarrangement of a third and a fourth capacitor (C_(3j), C_(4j)) coupledbetween the second input (IP_(2j)) and the second output (OP_(2j)), andan electrical coupling between a conjunction point of the third andfourth capacitors (C_(3j), C_(4j)) and a conjunction point of the twodiodes (D_(1j), D_(2j)).
 5. A voltage multiplier according to claim 1,characterized in that each multiplier stage (STG_(j)) comprises a firstcapacitor (C_(1j)) coupled between the first input (IP_(1j)) and thefirst output (OP_(1j)); each multiplier stage (STG_(j)) except for thefirst multiplier stage (STG₁) and the last multiplier stage (STG_(N))comprises a second capacitor (C_(2j)) coupled between the second input(IP_(2j)) and the second output (OP_(2j)), a series capacitorarrangement of a third and a fourth capacitor (C_(3j), C_(4j)) coupledbetween the second input (IP_(2j)) and the second output (OP_(2j)), anelectrical coupling between a conjunction point of the third and fourthcapacitors (C_(3j), C_(4j)), and a conjunction point of the two diodes(D_(1j), D_(2j)); the first multiplier stage (STG₁) comprises a secondcapacitor (C₄₁) coupled between the second output (OP₂₁) and aconjunction point of the two diodes (D₁₁, D₂₁); and the last multiplierstage (STG_(N)) comprises an electrical coupling between the secondinput (IP_(2N)), the second output (OP_(2N)), and a conjunction point ofthe two diodes (D_(1N), D_(2N)).
 6. A voltage multiplier according toclaim 1, characterized in that each multiplier stage (STG_(j)) comprisesa third input (IP_(3j)), a third output (OP_(3j)) which is coupled to arespective third input (IP₃₁) of another multiplier stage (STG_(j))except for the last multiplier stage (STG_(N)), which third input(IP_(3j)) of the first multiplier stage (STG₁) constitutes a third input(IVM₃) of the chain, each multiplier stage (STG_(j)) comprising afurther series diode arrangement of two diodes (D_(1jA), D_(2jA)) bothcoupled, in the same current conducting direction as in the series diodearrangement, between the first input (IP_(1j)) and the first output(OP_(1j)), a first capacitor (C_(2j)) coupled between the second input(IP_(2j)) and the second output (OP_(2j)), and a second capacitor(C_(2jA)) coupled between the third input (IP_(3j)) and the third output(OP_(3j)), and that in at least one of the multiplier stages (STG_(j))the equalizing means comprises a time dependent voltage level-shifter(VLS_(j)) coupled between the second output (OP_(2j)) and a conjunctionpoint of the two diodes (D_(1j), D_(2j)) of the series diodearrangement, and in the remaining multiplier stages the equalizing meanscomprises an electrical coupling between the second output (OP_(2j)) anda conjunction point of the two diodes (D_(1j), D_(2j)) of the seriesdiode arrangement, and in at least one of the multiplier stages(STG_(j)) the equalizing means comprises a further time dependentvoltage level-shifter (VLS_(jA)) coupled between the third output(OP_(3j)) and a conjunction point of the two diodes (D_(1jA), D_(2jA))of the further series diode arrangement, and in the remaining multiplierstages the equalizing means comprises an electrical coupling between thethird output (OP_(3j)) and a conjunction point of the two diodes(D_(1jA), D_(2jA)) of the further series diode arrangement.
 7. A voltagemultiplier according to claim 1, characterized in that each multiplierstage (STG_(j)) comprises a third input (IP_(3j)), a third output(OP_(3j)) which is coupled to a respective third input (IP_(3j)) ofanother multiplier stage (STG_(j)) except for the last multiplier stage(STG_(N)), which third input (IP₃₁) of the first multiplier stage (STG₁)of the chain constitutes a third input (IVM₃) of the chain, eachmultiplier stage (STG_(j)) comprising a further series diode arrangementof two diodes (D_(1jA), D_(2jA)) both coupled, in the same currentconducting direction as in the series diode arrangement, between thefirst input (IP_(1j)) and the first output (OP_(1j)), each multiplierstage (STG_(j)) except for the first multiplier stage (STG₁) comprises afirst capacitor (C_(2j)) coupled between the second input (IP_(2j)) andthe second output (OP_(2j)), and a second capacitor (C_(2jA)) coupledbetween the third input (IP_(3j)) and the third output (OP_(3j)), and inthat the first multiplier stage (STG₁) comprises a first electricalcoupling between the second input (IP₂₁) and the second output (OP₂₁),and a second electrical coupling between the third input (IP₃₁) and thethird output (OP₃₁), and that in at least one of the multiplier stages(STG_(j)) the equalizing means comprises a time dependent voltagelevel-shifter (VLS_(j)) coupled between the second output (OP_(2j)) anda conjunction point of the two diodes (D_(1j), D_(2j)) of the seriesdiode arrangement, and in the remaining multiplier stages the equalizingmeans comprises an electrical coupling between the second output(OP_(2j)) and a conjunction point of the two diodes (D_(1j), D_(2j)) ofthe series diode arrangement, and in at least one of the multiplierstages (STG_(j)) the equalizing means comprises a further time dependentvoltage level-shifter (VLS_(jA)) coupled between the third output(OP_(3j)) and a conjunction point of the two diodes (D_(1jA), D_(2jA))of the further series diode arrangement, and in the remaining multiplierstages the equalizing means comprises an electrical coupling between thethird output (OP_(3j)) and a conjunction point of the two diodes(D_(1jA), D_(2jA)) of the further series diode arrangement.
 8. A voltagemultiplier according to claim 1, characterized in that each multiplierstage (STG_(j)) comprises a third input (IP_(3j)), a third output(OP_(3j)) which is coupled to a respective third input (IP_(3j)) ofanother multiplier stage (STG_(j)) except for the last multiplier stage(STG_(N)), which third input (IP₃₁) of the first multiplier stage (STG₁)constitutes a third input (IVM₃) of the chain, each multiplier stage(STG_(j)) comprises a further series diode arrangement of two diodes(D_(1jA), D_(2jA)) both coupled, in the same current conductingdirection as in the series diode arrangement, between the first input(IP_(1j)) and the first output (OP_(1j)), a first capacitor (C_(2j))coupled between the second input (IP_(2j)) and the second output(OP_(2j)), a second capacitor (C_(2jA)) coupled between the third input(IP_(3j)) and the third output (OP_(3j)), a series capacitor arrangementof a third and a fourth capacitor (C_(3j), C_(4j)) coupled between thesecond input (IP_(2j)) and the second output (OP_(2j)); a further seriescapacitor arrangement of a fifth and a sixth capacitor (C_(3jA),C_(4jA)) coupled between the third input (IP_(3j)) and the third output(OP_(3j)), an electrical coupling between a conjunction point of thethird and fourth capacitors (C_(3j), C_(4j)) and a conjunction point ofthe two diodes (D_(1j), D_(2j)) of the diode arrangement, and a furtherelectrical coupling between a conjunction point of the fifth and sixthcapacitors (C_(3jA), C_(4jA)) and a conjunction point of the two diodes(D_(1jA), D_(2jA)) of the further diode arrangement.
 9. A voltagemultiplier according to claim 1, characterized in that each multiplierstage (STG_(j)) comprises a third input (IP_(3j)), a third output(OP_(3j)) which is coupled to a respective third input (IP_(3j)) ofanother multiplier stage (STG_(j)) except for the last multiplier stage(STG_(N)), which third input (IP₃₁) of the first multiplier stage (STG₁)constitutes a third input (IVM₃) of the chain, each multiplier stage(STG_(j)) comprises a further series diode arrangement of two diodes(D_(1jA), D_(2jA)) both coupled, in the same current conductingdirection as in the series diode arrangement, between the first input(IP_(1j)) and the first output (OP_(1j)), each multiplier stage(STG_(j)) except for the first multiplier stage (STG₁) and the lastmultiplier stage (STG_(N)) comprises a first capacitor (C_(2j)) coupledbetween the second input (IP_(2j)) and the second output (OP_(2j)), asecond capacitor (C_(2jA)) coupled between the third input (IP_(3j)) andthe third output (OP_(3j)), a series capacitor arrangement of a thirdand a fourth capacitor (C_(3j), C_(4j)) coupled between the second input(IP_(2j)) and the second output (OP_(2j)), a further series capacitorarrangement of a fifth and a sixth capacitor (C_(3jA), C_(4jA)) coupledbetween the third input (IP_(3j)) and the third output (OP_(3j)), anelectrical coupling between a conjunction point of the third and fourthcapacitors (C_(3j), C_(4j)) and a conjunction point of the two diodes(D_(1j), D_(2j)) of the series diode arrangement, a further electricalcoupling between a conjunction point of the fifth and sixth capacitors(C_(3jA), C_(4jA)) and a conjunction point of the two diodes (D_(1jA),D_(2jA)) of the further series diode arrangement, the first multiplierstage (STG₁) comprises a first capacitor (C₄₁) coupled between thesecond output (OP₂₁) and a conjunction point of the two diodes (D₁₁,D₂₁) of the series diode arrangement, and a second capacitor (C_(41A))coupled between the third output (OP₃₁) and a conjunction point of thetwo diodes (D_(11A), D_(21A)) of the further series diode arrangement,and the last multiplier stage (STG_(N)) comprises an electrical couplingbetween the second input (IP_(2N)), the second output (OP_(2N)), and theconjunction point of the two diodes (D_(1N), D_(2N)) of the series diodearrangement, a further electrical coupling between the third input(IP_(3N)), the third output (OP_(3N)), and a conjunction point of thetwo diodes (D_(1NA), D_(2NA)) of the further series diode arrangement.10. A voltage multiplier according to claim 2, characterized in that theat least one time dependent voltage level-shifter (VLS_(j)) comprises avoltage level-shift capacitor (C_(sj)).
 11. A voltage multiplieraccording to claim 2 characterized in that in each multiplier stage(STG_(j)) the equalizing means (VLS_(j)) comprises a time dependentvoltage level-shifter (VLS_(j)) comprising a voltage level-shiftcapacitor (C_(sj)).
 12. A voltage multiplier according to claim 3characterized in that in each multiplier stage (STG_(j)) except for thelast multiplier stage (STG_(N)) the equalizing means (VLS_(j)) comprisesa time dependent voltage level-shifter (VLS_(j)) comprising a voltagelevel-shift capacitor (C_(sj)).
 13. A voltage multiplier according toclaim 11, characterized in that all the capacitance values of thelevel-shift capacitors (C_(s1)-C_(sN)) are dimensioned in a manner that,during operation, the currents (I₁-I_(N)) through the diodes (D₁₁, D₂₁ .. . D_(1N), D_(2N)) have equal current distributions as a function oftime.
 14. A voltage multiplier according to claim 6, characterized inthat the at least one time dependent voltage level-shifter (VLS_(j))comprises a voltage level-shift capacitor (C_(sj)), and the at least onefurther time dependent voltage level-shifter (VLS_(jA)), whichcorresponds to a time dependent voltage level-shifter (VLS_(j))comprising a voltage level-shift capacitor (C_(sj)), comprises a furthervoltage level-shift capacitor (C_(sjA)).
 15. A voltage multiplieraccording to claim 6 characterized in that in each multiplier stage(STG_(j)) the equalizing means (VLS_(j)) comprises a time dependentvoltage level-shifter (VLS_(j)) comprising a voltage level-shiftcapacitor (C_(sj)), and a further time dependent voltage level-shifter(VLS_(jA)) comprising a further voltage level-shift capacitor (C_(sjA)).16. A voltage multiplier according to claim 7 characterized in that ineach multiplier stage (STG_(j)) except for the last multiplier stage(STG_(N)) the equalizing means (VLS_(j)) comprises a time dependentvoltage level-shifter (VLS_(j)) comprising a voltage level-shiftcapacitor (C_(sj)), and a further time dependent voltage level-shifter(VLS_(jA)) comprising a further voltage level-shift capacitor (C_(sjA)).17. A voltage multiplier according to claim 15, characterized in thatall the capacitance values of the level-shift capacitors (C_(s1)-C_(sN))are dimensioned in a manner that, during operation, the currents(I₁-I_(N)) through the diodes (D₁₁, D₂₁ . . . D_(1N), D_(2N)) of theseries diode arrangements have equal current distributions as a functionof time, and all the capacitance values of the further level-shiftcapacitors (C_(s1A)-C_(sNA)) are dimensioned in a manner that, duringoperation, the currents (I_(1A)-I_(NA)) through the diodes (D_(11A),D_(21A) . . . D_(1NA), D_(2NA)) of the further series diode arrangementshave equal current distributions as a function of time.
 18. A voltagemultiplier according to claim 4, characterized in that in eachmultiplier stage (STG_(j)) the capacitance values of the second, third,and fourth capacitors (C_(2j), C_(3j), C_(4j)) are dimensioned in amanner that, during operation, the currents (I₁-I_(N)) through theconducting diodes (D₁₁, D₂₁ . . . D_(1N), D_(2N)) have equal currentdistributions as a function of time.
 19. A voltage multiplier accordingto claim 5, characterized in that the capacitance value of the secondcapacitor (C₄₁) in the first multiplier (STG), and the capacitor valuesof the second, third, and fourth capacitors (C_(2j), C_(3j), C_(4j)) ineach multiplier stage (STG₂-STG_(N-1)) except in the first and the lastmultiplier stages (STG₁, STG_(N)) are dimensioned in a manner that,during operation, the currents (I₁-I_(N)) through the diodes (D₁₁, D₂₁ .. . D_(1N), D_(2N)) have equal current distributions as a function oftime.
 20. A voltage multiplier according to claim 8, characterized inthat in each multiplier stage (STG_(j)) the capacitance values of thefirst, second, and third capacitors (C₂₁, C₃₁, C₄₁) are dimensioned in amanner that, during operation, the currents (I₁-I_(N)) through thediodes (D₁₁, D₂₁ . . . D_(1N), D_(2N)) of the series diode arrangementshave equal current distributions as a function of time.
 21. A voltagemultiplier according to claim 9, characterized in that the capacitancevalue of the first capacitor (C₄₁) in the first multiplier (STG), andthe capacitor values of the first, second, and third capacitors (C_(2j),C_(3j), C_(4j)) in each multiplier stage (STG₂-STG_(N-1)) except in thefirst and the last multiplier stages (STG₁, STG_(N)) are dimensioned ina manner that, during operation, the currents (I₁-I_(N)) through thediodes (D₁₁, D₂₁ . . . D_(1N), D_(2N)) of the series diode arrangementshave equal current distributions as a function of time.
 22. A voltagemultiplier according to claim 1, characterized in that the voltagemultiplier further comprises a smoothing capacitor (C₀) coupled betweenthe first output (OP_(1N)) of the last multiplier stage (STG_(N)) andthe first input (IP₁₁) of the first multiplier stage (STG₁). 23.Apparatus comprising a device for generating a high voltage,characterized in that the device for generating the high voltagecomprises a voltage multiplier (VM) as defined in claim
 1. 24. Apparatuscomprising an X-ray tube (XRT) for generating X-rays comprising a devicefor generating a high voltage for the X-ray tube (XRT), characterized inthat the device for generating the high voltage comprises a voltagemultiplier (VM) as defined in claim
 1. 25. Apparatus comprising acathode ray tube (CRT) for generating an image on a screen (SCR)comprising a device for generating a high voltage for the cathode raytube (CRT), characterized in that the device for generating the highvoltage comprises a voltage multiplier (VM) as defined in claim 1.